Presently, a great deal of emphasis is given in designing electronic circuits having lower area and power requirements. For such lower area and power requirements, employing single power supply voltages (e.g., either a single positive or single negative supply voltage) in the electronic circuits may also be considered in certain cases. In these electronic circuits, sometimes, real world signals may be in conflict with supply range provided by the single power supply. For example, a sample and hold circuit operating on a single positive voltage supply may be required to sample input voltages less than a ground voltage (Substrate potential).
In such type of sample and hold circuits, gate bootstrapped MOS switches (either PMOS or NMOS) are used. However, such sampling schemes have a number of operating constraints especially when they handle voltages below ground potential. For example, reliability should be maintained between the supply voltage and range of input voltages that is to be sampled. Further, linearity of such switches may be maintained by minimizing ON state switch resistance (by maximizing the gate overdrive of the MOS switches) and by ensuring that there should not be leakage current between terminals of the MOS switches during sample and hold phases.